features 14-bit resolution 3mpps throughput rate (14-bits) functionally complete very low noise excellent signal-to-noise ratio edge triggered small, 40-pin, tdip package low power, 500mw typical low cost programmable analog bandwidth the adcds-1403 is an application-speci? c video signal processor designed for electronic- imaging applications that employ ccd's (charge coupled devices) as their photodetector. the adcds-1403 incorporates a "user con? gurable" input ampli? er, a cds (correlated double sampler) and a sampling a/d converter in a single package, providing the user with a complete, high perfor- mance, low-cost, low-power, integrated solution. the key to the adcds-1403's performance is a unique, high-speed, high-accuracy cds circuit, which eliminates the effects of residual charge, charge injection and "kt/c" noise on the ccd's output ? oating capacitor, producing a "valid video" output signal. the adcds-1403 digitizes this resultant "valid video" signal using a high-speed, low-noise sampling a/d converter. the adcds-1403 requires only the rising edge of start convert pulse to initiate its conversion process. additional features of the adcds-1403 include gain adjust, offset adjust, precision +2.4v reference, and a programmable analog bandwidth function. product overview 4 3 2 26 inverting input direct input offset adjust reference hold 27 32, 33 7, 35, 37 data valid digital ground analog ground 25 23 10 24 6 start convert bit 1 (msb) bit 14 (lsb) out-of-range +2.4v reference outpu t +12v a C5v a +5v a +5v d 39 38 36 34 timing and control sampling a/d non-inverting input 75 523 0.01f 5k 1 fine gain adjust 5 input amplifier 30 31 a1 correlated double sampler a? input/output connections pin function pin function 1 fine gain adjust 40 no connect 2 offset adjust 39 +12v 3 direct input 38 C5va 4 inverting input 37 analog ground 5 non-inverting input 36 +5va 6 +2.4v ref. output 35 analog ground 7 analog ground 34 +5vd 8 no connect 33 digital ground 9 no connect 32 digital ground 10 bit 14 (lsb) 31 a1 11 bit 13 30 a? 12 bit 12 29 no connect 13 bit 11 28 no connect 14 bit 10 27 data valid 15 bit 9 26 reference hold 16 bit 8 25 start convert 17 bit 7 24 out-of-range 18 bit 6 23 bit 1 (msb) 19 bit 5 22 bit 2 20 bit 4 21 bit 3 figure 1. adcds-1403 functional block diagram adcds-1403 14-bit, 3 megapixels/second imaging signal processor ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 adcds-1403.b02 page 1 of 9
absolute maximum ratings functional speci? cations the following speci? cations apply over the operating temperature range, under the follow- ing conditions: vcc=+12v, +vdd=+5v, vee=C5v, ? n=98khz, sample rate=3mhz. parameters min. typ. max. units +12v supply (pin 32) 0 +14 volts C5v supply (pin 38) C6.5 +0.3 volts +5v supply (pin 34, 36) C0.3 +6.5 volts digital input (pin 25, 26, 30, 31) C0.3 vdd+0.3v volts analog input (pin 3,4,5) C6 +6 volts lead temperature (10 seconds) 300 c analog input min. typ. max. units input voltage range (externally con? gurable) 0.350 2.8 volts p-p input resistance 5000 ohm input capacitance 10 pf digital inputs logic level logic 1 +3.5 volts logic 0 +.80 volts logic loading logic 1 +10 ua logic 0 C10 ua digital outputs logic levels logic 1 (ioh = .5ma) +2.4 volts logic 1 (ioh = 50a) +4.5 volts logic 0 (iol = 1.6ma) +0.4 volts logic 0 (iol = 50ua) +0.1 volts internal reference voltage (fine gain adjust pin (1) grounded) +25c 2.35 2.4 2.45 volts 0 to 70c 2.35 2.4 2.45 volts C55 to +125c 2.35 2.4 2.45 volts external current 1.0 ma static performance differential nonlinearity (histogram, 98khz) +25c C0.90 0.5 +.90 lsb 0 to 70c C0.90 0.5 +.90 lsb C55 to +125c C1.0 0.6 +1.0 lsb integral nonlinearity +25c 2.5 lsb 0 to 70c 2.5 lsb C55 to +125c 2.5 lsb guaranteed no missing codes 0 to 70c 14 lsb C55 to +125c 14 lsb dc noise +25c 1.0 1.6 lsb 0 to 70c 1.0 2.0 lsb C55 to +125c 1.25 2.5 lsb offset error +25c 0.6 1.25 %fsr 0 to 70c 0.6 1.25 %fsr C55 to +125c 0.6 1.45 %fsr gain error +25c 1.00 2.8 %fsr 0 to 70c 1.35 2.8 %fsr C55 to +125c 1.35 2.8 %fsr dynamic performance min. typ. max. units reference hold aquisition time 100 ns droop @ +25c 25 mv/us @ C55 to +125c 100 mv/us peak harmonic (sfdr) (cdd-in, input on pin (3) input @ 98khz) @ +25 c C76 db @ 0 to +70c C76 db @ C55 to +125c C74 db peak harmonic (sfdr) (input on pin (5) input @ 98khz) @ +25 c C76 db @ 0 to +70c C76 db @ C55 to +125c C74 db total harmonic distortion (cdd-in, input on pin (3) input @ 98khz) @ +25 c C75 db @ 0 to +70c C75 db @ C55 to +125c C74 db (input on pin (5) input @ 98khz) @ +25 c C76 db @ 0 to +70c C76 db @ C55 to +125c C74 db signal-to-noise ratio without distortion (cdd-in, input on pin (3) input @ 98khz) @ +25 c 73 75 db @ 0 to +70c 73 75 db @ C55 to +125c 70 73 db (input on pin (5) input @ 98khz) @ +25 c 73 75 db @ 0 to +70c 73 75 db @ C55 to +125c 70 73 db signal-to-noise ratio with distortion (cdd-in, input on pin (3) input @ 98khz) @ +25 c 71 db @ 0 to +70c 71 db @ C55 to +125c 70 db (input on pin (5) input @ 98khz) @ +25 c 71 db @ 0 to +70c 71 db @ C55 to +125c 70 db signal timing conversion rate C55 to +125c 3 mhz conversion time 200 nsec start convert pulse width 20 150 nsec power requirements power supply range +12v supply +11.4 +12.0 +12.6 volts +5v supply +4.75 +5.0 +5.25 volts C5v supply C4.75 C5.0 C5.25 volts adcds-1403 14-bit, 3 megapixels/second imaging signal processor ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 adcds-1403.b02 page 2 of 9
technical notes 1. obtaining fully speci? ed performance from the adcds-1403 requires careful attention to pc-card layout and power supply decoupling. the device's analog and digital grounds are connected to each other internally. depending on the level of digital switching noise in the overall ccd system, the performance of the adcds-1403 may be improved by connecting all ground pins (7,32,33,35, 37) to a large analog ground plane beneath the package. the use of a single +5v analog supply for both the +5v a (pin 36) and +5v d (pin 34) may also be bene? cial. 2. bypass all power supplies to ground with a 4.7f tantalum capacitor in parallel with a 0.1f ceramic capacitor. locate the capacitors as close to the package as possible. 3. if using the suggested offset and gain adjust circuits (figure 3 & 5), place them as close to the adcds-1403's package as possible. 4. a0 and a1 (pins 30, 31) should be bypassed with 0.1f capacitors to ground to reduce susceptibility to noise. adcds-1403 modes of operation the input ampli? er stage of the adcds-1403 provides the designer with a tremendous amount of ? exibility. the architecture of the adcds- 1403 allows its input-ampli? er to be con? gured in any of the following con? gurations: ? direct mode (ac coupled) ? non-inverting mode ? inverting mode when applying inputs which are less than 2.8vp-p, a coarse gain adjustment (applying an external resistor to pin 4) must be performed to ensure that the full scale video input signal (saturated signal) produces a 2.8vp-p signal at the input-ampli? er's output (v out ). in all three modes of operation, the video portion of the signal at the cds input (i.e. input-ampli? er's v out ) must be more negative than its asso- ciated reference level and v out should not exceed 2.8v dc. the adcds-1403 achieves it speci? ed accuracies without the need for external calibration. if required, the device's small initial offset and gain errors can be reduced to zero using the fine gain adjust (pin1) and offset adjust (pin 2) features. figure 2a. figure 2b. 4 3 5 75 523 v in no connect v out = 2.8vp-p 5k 0.01f rext 4 3 5 75 523 v in no connect v out = 2.8vp-p 5k 0.01f rext figure 2c. 4 3 5 75 523 v in no connect v out = 2.8vp-p 5k 0.01f direct mode (ac coupled) this is the most common input con? guration as it allows the adcds- 1403 to interface directly to the output of the ccd with a minimum amount of analog "front-end" circuitry. this mode of operation is used with full- scale video input signals from 0.350vp-p to 2.8vp-p. figure 2a. describes the typical con? guration for applications using a video input signal with a maximum amplitude of 0.350vp-p. the coarse gain of the input ampli? er is determined from the following equation: v out = 2.8vp-p = v in *(1+(523/75)), with all internal resistors having a 1% tolerance. additional ? ne gain adjustment can be accomplished using the fine gain adjust (pin 1 see figure 5). figure 2b. describes the typical con? guration for applications using a video input signal with an amplitude greater than 0.350vp-p and less than 2.8vp-p. using a single external series resistor (see figure 4.), the coarse gain of the adcds-1403 can be set, with additional ? ne gain adjustments being made using the fine gain adjust function (pin 1 see figure 5). the coarse gain of the input ampli? er can be determined from the following equation: v out = 2.8vp-p = v in *(1+(523/(75+rext))), with all internal resistors having a 1% tolerance. power requirements min. typ. max. units power supply current +12v supply +13 +16 ma power supply current +5v supply +40 +46 ma C5v supply C27 C35 ma power dissipation 0.50 0.60 watts power supply rejection (5%) @ +25c 0.02 0.03 %fsr/%v environmental operating temperature range adcds-1403 0 +70 c ADCDS-1403EX C55 +125 c storage temperature C65 +150 c package type 40-pin, tdip weight 16.10 grams adcds-1403 14-bit, 3 megapixels/second imaging signal processor ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 adcds-1403.b02 page 3 of 9
inverting mode the inverting mode of operation can be used in applications where the analog input to the adcds-1403 has a video input signal whose amplitude is more positive than its associated reference level. the adcds-1403's correlated double sampler (i.e. input ampli? er's v out ) requires that the video signal's amplitude be more negative than its reference level at all times (see timing diagram for details). using the adcds-1403 in the inverting mode allows the designer to perform an additional signal inver- sion to correct for any analog "front end" pre-processing that may have occurred prior to the adcds-1403. figure 2e. describes the typical con? guration for applications using a video input signal with a maximum amplitude of 0.350vp-p. additional ? ne gain adjustments can be made using the fine gain adjust function (pin 1). the coarse gain of this circuit can be determined from the following equation: v out = 2.8vp-p = Cv in *(523/75), with all internal resistors having a 1% tolerance. figure 2f. describes the typical con? guration used in applications needing to invert video input signals whose amplitude is greater than 0.350vp-p. using a single external series resistor (see figure 4.), the initial gain of the adcds-1403 can be set, with additional ? ne gain adjustments being made using the fine gain adjust function (pin 1). the coarse gain of this circuit can be determined from the following equation: v out = 2.8vp-p = Cv in *(523/75+rext), with all internal resistors having a 1% tolerance. figure 4. coarse gain adjustment plot non-inverting mode the non-inverting mode of the adcds-1403 allows the designer to either attenuate or add non-inverting gain to the video input signal. this con? guration also allows bypassing the adcds-1403's internal coupling capacitor, allowing the user to provide an external capacitor of appropriate value. figure 2c. describes the typical con? guration for applications using video input signals with amplitudes greater than 0.350vp-p and less than 2.8vp-p (with common mode limit of 2.5v dc). using a single external series resistor (see figure 4.), the coarse gain of the adcds-1403 can be set with additional ? ne gain adjustments being made using the fine gain adjust function (pin 1 see figure 5). the coarse gain of the circuit can be determined from the following equation: v out = 2.8vp-p = v in *(1+(523/(75+rext))), with all internal resistors having a 1% tolerance. figure 2d. describes the typical con? guration for applications using a video input signal whose amplitude is greater than 2.8vp-p. using a single external series resistor (rext 1) in conjunction with the internal 5k (1%) resistor to ground, an attenuation of the input signal can be achieved. additional ? ne gain adjustments being made using the fine gain adjust function (pin 1). the coarse gain of this circuit can be determined from the following equation: v out = 2.8vp-p = [v in *(5000/(rext1+5000))]* [1+(523/(75+rext2))], with all internal resistors having a 1% tolerance. figure 2d. figure 2e. 4 3 5 75 523 no connect v out = 2.8vp- p 5k 0.01f rext1 v in rext2 4 3 5 75 523 no connect v out = 2.8vp-p 5k 0.01f Cv in 4 3 5 75 523 no connect v out = 2.8vp- p 5k 0.01f C v in rext figure 2f. figure 3. offset adjustment circuit offset adjust 2 external series resistor adcds-1403 +5v C5v 20k coarse gain adjustment plot external gain resistor vs. full scale video input 10 100 1000 10000 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 full scale video signal (volts) external gain resistor (ohms) inverting mode direct mode & non-inverting mode adcds-1403 14-bit, 3 megapixels/second imaging signal processor ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 adcds-1403.b02 page 4 of 9
figure 6. offset adjustment vs. external series resistor offset adjustment vs. external series resistor 10 100 1000 10000 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60 k external series resistor (ohm's) lsb's of adjustment figure 5. fine gain adjustment circuit adcds-1403 fine gain adjust 1 +5v C5v 2 0k external series resistor value ( ohms ) 0.01 0.1 1 10 100 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k offset adjustment sensitivity external series resistor vs. output variation (lsb's) output variation (lsb's) peak-peak variation at potentiometer 1mv 10mv 100mv figure 7. offset adjustment sensitivity offset adjustment manual offset adjustment for the adcds-1403 can be accomplished using the adjustment circuit shown in figure 3. a software controlled d/a converter can be substituted for the 20k potentiometer. the offset adjustment feature allows the user to adjust the offset/dark current level of the adcds-1403 until the output bits are 00 0000 0000 0000 and the lsb ? ickers between 0 and 1. offset adjust should be performed before gain adjust to avoid interaction. the adcds-1403's offset adjustment is dependent on the value of the external series resistor used in the offset adjust circuit (figure 3). the offset adjustment graph (figure 6) illustrates the typical relationship between the external series resistor value and its offset adjustment capability utilizing 5v supplies. offset adjustment sensitivity it should be noted that with increasing amounts of offset adjustment (smaller values of external series resistors), the adcds-1403 becomes more susceptible to power supply noise or voltage variations seen at the wiper of the offset potentiometer. for example: external 50k resistor: 1. 10mv of noise or voltage variation at the potentiometer will produce 0.25lsb's of output variation. 2. 100mv of noise or voltage variation at the potentiometer will produce 2.5lsb's of output variation. the offset adjustment sensitivity graph (figure 7) illustrates the offset adjustment sensitivity over a wide range of external resistor and noise values. if a large offset voltage is required, it is recommended that a very low noise external reference be used in the offset adjust circuit in place of power supplies. the adcds-1403's +2.4v reference output could be con? gured to provide the reference voltage for this type of application. fine gain adjustment fine gain adjustment (pin 1) is provided to compensate for the toler- ance of the external coarse gain resistor (rext) and/or the unavailability of exact coarse gain resistor (rext) values. note, the ? ne gain adjustment will not change the expected input ampli? er's full scale v out (2.8vp-p.) instead, the gain of the adcds-1403's internal a/d is adjusted allowing the actual input ampli? er's full scale v out to produce an output code of all ones (11 1111 1111 1111). fine gain adjustment for the adcds-1403 is accomplished using the adjustment circuit shown below (figure 5). a software controlled d/a converter can be substituted for the 20k potentiometer. the ? ne gain adjust circuit ensures that the video input signal (saturated signal) will be properly scaled to obtain the desired full scale digital output of 11 1111 1111 1111, with the lsb ? ickering between 0 and 1. fine gain adjust should be performed following the offset adjust to avoid interaction. the ? ne gain adjust provides 256 codes of adjust when 5v supplies are used for the fine gain adjust circuit. adcds-1403 14-bit, 3 megapixels/second imaging signal processor ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 adcds-1403.b02 page 5 of 9
table 1. out-of-range conditions table 2. output coding out of range msb over range under range input signal 0 0 0 0 in range 0 1 0 0 in range 1 0 0 1 underrrange 1 1 1 0 overrange notes: ? input ampli? er v out = (video signal - reference level) ? the video portion of the differential signal (input-ampli? er's v out ) must be more negative than its associated reference level and v out should not exceed 2.8v dc. input amplifier vout, ? (volts p-p) scale digital output out-of-range video signal-reference signal > C2.80000 >full scale C1lsb 11 1111 1111 1111 1 C2.80000 full scale C1lsb 11 1111 1111 1111 0 C2.10000 3/4fs 11 0000 0000 0000 0 C1.40000 1/2fs 10 0000 0000 0000 0 C0.70000 1/4fs 01 0000 0000 0000 0 C0.35000 1/8fs 00 1000 0000 0000 0 C0.000171 1 lsb 00 0000 0000 0001 0 0 0 00 0000 0000 0000 0 video signal-reference signal <0 ? <0 00 0000 0000 0000 1 output coding the adcds-1403's output coding is straight binary as indicated in table 2. the table shows the relationship between the output data coding and the difference between the reference signal voltage and its correspond- ing video signal voltage. (these voltages are referred to the output of the adcds-1403's input ampli? er's v out ). programmable analog bandwidth function when interfacing to ccd arrays with very high-speed "read-out" rates, the adcds-1403's input stage must have suf? cient analog bandwidth to accurately reproduce the output signals of the ccd array. the amount of analog bandwidth determines how quickly and accurately the "reference hold" and the "cds output" signals will settle. if only a single analog band- width was offered, the adcds-1403's bandwidth would be set to acquire and digitize ccd output signals to 14-bit accuracy, at maximum conversion rate of 3mhz (333ns see figure 11. for details). applications not requiring the maximum conversion rate would be forced to use the full analog band- width at the possible expense of noise performance. the adcds-1403 avoids this situation by offering a fully programmable analog bandwidth function. the adcds-1403 allows the user to "bandwidth limit" the input stage in order to realize the highest level of noise perfor- mance for the application being considered. table 3. describes how to select the appropriate reference hold "aquisition time" and cds output "settling time" needed for a particular application. each of the selections listed in table 3. have been optimized to provide only enough analog bandwidth to acquire a full scale input step, to 14-bit accuracy, in a single conversion. increasing the analog bandwidth (using a faster settling and acquisition time) would only serve to potentially increase the amount of noise at the adcds-1403's output. the adcds-1403 uses a two bit digital word to select four different analog bandwidths for the adcds-1403's input stage (see table 3. for details). msb out-of-range "overrange" "underrange" figure 8. overrange/ underrange circuit out-of-range indicator the adcds-1403 provides a digital out-of-range output signal (pin 24) for situations when the video input signal (saturated signal) is beyond the input range of the internal a/d converter. the digital output bits and the out-of-range signal correspond to a particular sampled video input voltage, with both of these signals having a common pipeline delay. using the circuit described in figure 8., both overrange and under- range conditions can be detected (see table 1). when combined with a d/a converter, digital detection and orrection can be performed for both the gain and offset errors. adcds-1403 14-bit, 3 megapixels/second imaging signal processor ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 adcds-1403.b02 page 6 of 9
table 3. programmable analog bandwidth reference hold "acquisition time" cds output "settling time" a0 (pin 30) a1 (pin 31) adcds-1403 maximum conversion rate C3db bw 100ns 120ns 0 0 3mhz 10.5mhz 200ns 250ns 1 0 2mhz 6.6mhz 450ns 500ns 0 1 1mhz 3.7mhz 600ns 1000ns 1 1 0.5mhz 2.5mhz note: see figure 11. for timing details timing the adcds-1403 requires two independently operated signals to accu- rately digitize the analog output signal from the ccd array. ? reference hold (pin 26) ? start convert (pin 25) the "reference hold" signal controls the operation of an internal sample-hold circuit. a logic "1" places the sample-hold into the hold mode, capturing the value of the ccd's reference signal. the reference hold signal allows the user to control the exact moment when the sample-hold is placed into the "hold" mode. for optimal performance the sample-hold figure 9. adcds-1403 connection diagram should be placed into the "hold" mode once the reference signal has fully settled from all switching transients to the desired accuracy (user de? ned). once the reference signal has been "held" and the video portion of the ccd's analog output signal appears at the adcds-1403's input, the adcds-1403's correlated double sampler produces a "cds output" signal (see figure 11.) which is the difference between the "held" reference level and its associated video level. when the "cds output" signal has settled to the desired accuracy (user de? ned), the a/d conversion process can be initiated with the rising edge of a single start convert (pin 25) signal. + + + +12v +5vd C5va 4.7f 0.1f 39 36 38 1 20k +5v C5v 5 4 3 23 22 21 20 19 18 17 16 15 14 13 12 11 10 bit 1 (msb) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 (lsb) 6 24 27 +2.4v reference out out-of-range data valid adcds-1403 4.7f 0.1f 4.7f 0.1f analog ground non-inverting input inverting input direct input +5va 36 7, 35, 37 + 4.7f 0.1f 26 25 ref. hold start convert 2 20k +5v C5v offset adjust fine gain adjust external series resistor 32, 33 digital ground 30 31 a1 a 0.1f 0.1f adcds-1403 14-bit, 3 megapixels/second imaging signal processor ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 adcds-1403.b02 page 7 of 9
figure 11. adcds-1403 timing diagram figure 10. reference hold timing once the a/d conversion has been initiated, reference hold (pin 26) can be placed back into the "acquisition" mode in order to begin aquiring the next reference level. for optimal performance the adcds-1403's internal sample-hold should be placed back into the "aquisition" mode (reference hold to logic "0") during the ccd's "reference quiet time" ("reference quiet time" is de? ned as the period when the ccd's reference signal has settled from all switching transients to the desired accuracy (see figure 10.)). placing the sample-hold back into the "aquisition" mode during the "reference quiet time" prevents the adcds-1403's internal ampli? ers from unecessarily tracking (reproducing) the large switching transients that occur during the ccd's reset to reference transition. ccd output reference hold note: for optimal performance (fastest acquisition time), the adcds-1403 should be placed into the acquisition mode (reference hold to logic "0") during the ccd output's reference "quiet time". reference "quiet time" is defined as the period when the reference signal's swi tching transients have settled to an acceptable (user defined) accuracy. hold reset video reference reference "quiet time" 100ns min. acquisition time acquisition mode during reference "quiet time" reset n reset n+1 reset n+2 reset n+3 reset n+4 note: as described in figure 10, the 60ns min. is dependant on the quality of the ccd's reference when the adcds-1403 is switch ed back into the track mode ccd output start convert reference hold in cds output data output 100ns min. 133ns min 120ns min settling line full scale step 150ns min data n-4 valid data n-3 valid data n-2 valid data n-1 valid data n valid 20ns min n ref n video n ref. n+1 video n+1 100ns min. 333ns min. 120ns min. settling time 150ns typ. 20ns max ref. n video n video n+1 ref. n+2 video n+1 video n+2 ref. n+3 video n+1 video n+3 ref. n+4 n+2 n+3 n n+1 n+2 n+3 hold acquisition time n+1 invalid data 30ns min., 50ns max. data valid adcds-1403 14-bit, 3 megapixels/second imaging signal processor ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 adcds-1403.b02 page 8 of 9
ordering information operating 40-pin model temperature range package adcds-1403 0 to 70c tdip ADCDS-1403EX C55 to 125c tdip 0.100 typ. (2.540) 2.24 typ. (56.90) 0.900 0.010 (22.86) 1.900 0.008 (48.260) 0.23 typ. (5.84) 1.27 typ. (32.25) ? ? adcds-1403 14-bit, 3mhz imaging signal processor made in usa adcds-1403 14-bit, 3 megapixels/second imaging signal processor . makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained her ein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subject to change without notice. www.datel.com ? e-mail: help@datel.com ?? datel 11 cabot boulevard, mans? eld, ma 02048-1151 usa itar and iso 9001/14001 registered 31 mar 2011 adcds-1403.b02 page 9 of 9
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